Dr. Bharat Garg

Designation:

Assistant Professor

Specialization:

Signal Processing

Email:

bharat.garg@thapar.edu

Contact No.

+91-9407-363-919, +91-7974-677-918

Membership of Professional Institutions, Associations, Societies

Student Member, IEEE, from June 2017- till date

Publications and other Research Inputs

SCI/SSCI

  1. Bharat Garg, Sunil Dutt, and G. K. Sharma "Bit-width-aware constant-delay run-time Accuracy Programmable Adder for error-resilient applications" Microelectronics Journal, Elsevier 2016, Vol. 50, pp. 1-7
  2. Bharat Garg, and G. K. Sharma "A quality-aware Energy-scalable Gaussian Smoothing Filter for image processing applications" Microprocessors and Microsystems Elsevier (2016) Vol. 45, pp. 1-9.
  3. Nawandar, Neha, Bharat Garg, and G. K. Sharma, “RICO: A low power Repetitive Iteration CORDIC for DSP applications in portable devices”, System Architecture, Elsevier 2016, Vol 70, pp. 82-92.
  4. Bharat Garg and G. K. Sharma, “ACM: An Energy-efficient Accuracy Configurable Multiplier for Error-resilient Applications”, Journal of Electronics Testing, vol. 34, pp. 1-11, 2017.

Awards and Honours

  1. Got Design Productivity Win for “Automate Test Generation” at Cypress Semiconductors.
  2. Qualified GATE-2004, GATE-2012, GATE-2016, UGC-NET 2013, and UG-NET 2014

Description of Research Interests

  • Energy Efficient VLSI Architectures for Signal Processing Applications
  • Hardware Security

Journal Publications (SCI/SCIE)

  • J1. Vijaypal Rathor, Bharat Garg and G. K. Sharma, “A Novel Low Complexity Logic Encryption Technique for Design-for-Trust”, IEEE Transactions on Emerging Topics in Computing, 2018.
  • J2. Vijaypal Rathor, Bharat Garg and G. K. Sharma “New Lightweight Architectures for Secure FSM Design to Thwart Fault Injection and Trojan Attacks”, Journal of Electronics Testing, Vol. 34 (6), 2018.
  • J3. Vijaypal Rathor, Bharat Garg and G. K. Sharma, “New Light Weight Threshold Voltage Defined Camouflaged Gates for Trustworthy Designs”, Journal of Electronics Testing, Vol. 33, 2017.
  • J4. Bharat Garg, and G. K. Sharma, “ACM: An Energy-efficient Accuracy Configurable Multiplier for Error-resilient Applications”, Journal of Electronics Testing, Vol. 33, 2017
  • J5. Bharat Garg, Sunil Dutt, and G. K. Sharma "Bit-width-aware constant-delay run-time Accuracy Programmable Adder for error-resilient applications" Microelectronics Journal, Elsevier 2016, Vol. 50, pp. 1-7
  • J6. Bharat Garg, and G. K. Sharma "A quality-aware Energy-scalable Gaussian Smoothing Filter for image processing applications" Microprocessors and Microsystems Elsevier (2016) Vol. 45, pp. 1-9.
  • J7. Neha Nawandar, Bharat Garg, and G. K. Sharma, “RICO: A low power Repetitive Iteration CORDIC for DSP applications in portable devices”, System Architecture, Elsevier 2016, Vol 70, pp. 82-92.

Conference Publications:

  • C1. Bharat Garg, Nitesh K. Bharadwaj, and G. K. Sharma "Energy scalable approximate DCT architecture trading quality via boundary error-resiliency", System-on-Chip Conference (SOCC), 27th IEEE Int., 2014, Las Vegas, USA.
  • C2. Ankur Jaiswal, Bharat Garg, Vikas Kaushal, and G. K. Sharma, “SPAA-Aware 2D Gaussian Smoothing Filter Design Using Efficient Approximation Techniques”, In VLSI Design (VLSID), 2015 28th International Conference on pp. 333-338, IEEE, 2015.
  • C3. Vikas Kaushal, Bharat Garg, Ankur Jaiswal, and G. K. Sharma "Energy Aware Computation Driven Approximate DCT Architecture for Image Processing" In VLSI Design (VLSID), 2015 28th Int. Conf. on, pp. 357-362. IEEE, 2015
  • C4. Bharat Garg, Chaitanya Goteti, and G. K. Sharma, “A Low-Cost Energy Efficient Image Scaling Processor for Multimedia Applications”, International Symposium on VLSI Design and Test (VDAT-2016), pp. 1-6, 2016.
  • C5. Bharat Garg, Sameer Yadav, and G. K. Sharma, “An Area and Performance Aware ECG Encoder Design for Wireless Healthcare Services”, International Symposium on VLSI Design and Test (VDAT-2016), pp. 1-6, 2016.
  • C6. Bharat Garg, and G. K. Sharma, “Low Power Signal Processing via Approximate Multiplier for Error-Resilient Applications”, In Industrial and Information Systems (ICIIS-2016), 11th Int. Conference on, pp. 1-6, 2016.
  • C7. Bharat Garg, and G. K. Sharma, “Block Matching Algorithm for Deriving Quality-Tuneable Motion Estimation Architecture”, In Industrial and Information Systems (ICIIS-2016), 11th Int. Conference on, pp. 1-6, 2016.
  • C8. Naushad Ali and Bharat Garg, “New Energy Efficient Reconfigurable FIR Filter Architecture and Its VLSI Implementation”, International Symposium on VLSI and Test (VDAT-2017), pp. 1-6, 2017.
  • C9. Vijaypal Rathor, Bharat Garg and G. K. Sharma, “An Energy−Efficient Trusted FSM Design Technique to Thwart Fault Injection and Trojan Attacks”, In VLSI Design (VLSID), 2015 31st Int. Conf. on, pp. 73-78. IEEE, 2018.