Dr. Bharat Garg

Dr. Bharat Garg

Designation:

Assistant Professor

Specialization:

Signal Processing

Email:

bharat.garg@thapar.edu

Biography

Dr. Bharat Garg is working with ECED Department, Thapar Institute of Engineering and Technology, Patiala since 2017. He has completed her PhD degree in VLSI Circuits and Systems from ABV-Indian Institute of Information Technology and Management Gwalior in September 2017. His research interests include Low Power VLSI Design, Energy Efficient Architectures for Image/Signal Processing and Hardware Security.

Education

  • Ph.D. from ABV-Indian Institute of Information Technology and Management Gwalior in Energy Efficient VLSI Architectures for Image Processing
  • M. Tech in VLSI Design from ABV-Indian Institute of Information Technology and Management Gwalior
  • B.E. in Electronics Engineering from Proudyogiki Vishwavidyalaya Bhopal

Experience: Total Experience is more than 7 years in Teaching and more than 3 years in Industries.

  • March 2018 &ndash till date: Assistant Professor, ECED, Thapar Institute of Engineering and Technology, Patiala.
  • July 2017 &ndash March 2018: Lecture, ECED, Thapar Institute of Engineering and Technology, Patiala.
  • Aug 2011 – Aug 2012: Assistant Professor, Electronics and Communications Engineering Department, SRCEM, Banmore.
  • Feb 2010 – Aug 2011: Assistant Professor, Electronics and Communications Engineering Department, MPCT, Gwalior.
  • July 2009 – Jan 2010: ASIC Engineer, Incube Solutions India Pvt. Ltd., Hyderabad.
  • July 2007 – April 2009: Electrical Design Engineer, Cypress Semiconductors India Pvt. Ltd., Hyderabad.
  • July 2003 – July 2005: Lecturer, Electronics and Communications Engineering Department, MPCT, Gwalior.
  • Jan 2003 – June 2003: Lecturer, Electronics and Communications Engineering Department, Institute of Engineering, Jiwaji University, Gwalior.

Teaching Interests:

  • CMOS Circuit Design
  • Digital Signal Processing
  • VLSI Testing and Testability
  • FPGA Based System Design
  • Digital VLSI Design

Research Interest:

  • Low Power VLSI Design
  • VLSI Architectures for Image Processing
  • High Performance Arithmetic Unit Design
  • Hardware Security

Publications:

Journals

  1. Sujit Patel, Bharat Garg, and Shireesh Kumar Rai “Power and Area Efficient Approximate Carry Skip Adder for Error Resilient”, Turkish Journal of Electronics and Computer Engineering (Accepted) (SCI indexed).
  2. Shireesh Kumar Rai, Rishikesh Pandey and Bharat Garg, “Design of current differencing transconductance amplifier using novel technique of transconductance boosting for high frequency applications”, Journal of Circuits, Systems and Computers World Scientific (2019) (SCI indexed).
  3. Bharat Garg, S. Rai, Aakash Puranik and G. K. Sharma, “ES-COINA: An Energy Scalable Quality Aware Colour Interpolation Architecture”, Microprocessors and Microsystems Elsevier, Vol. 67, pp. 8-17, 2019 . (SCI indexed).
  4. Bharat Garg, and G. K. Sharma, “A process tolerant low-power adder architecture for image processing applications”, Turkish Journal of Electronics and Computer Engineering, Vol. 27 (3), pp. 1839-1854, 2019 (SCI indexed).
  5. Vijaypal Rathor, Bharat Garg and G. K. Sharma, “A Novel Low Complexity Logic Encryption Technique for Design-for-Trust”, IEEE Transactions on Emerging Topics in Computing, 2018 (SCI indexed)
  6. Vijaypal Rathor, Bharat Garg and G. K. Sharma “New Lightweight Architectures for Secure FSM Design to Thwart Fault Injection and Trojan Attacks”, Journal of Electronics Testing, Vol. 34 (6), 2018 (SCI Indexed).
  7. Vijaypal Rathor, Bharat Garg and G. K. Sharma, “New Light Weight Threshold Voltage Defined Camouflaged Gates for Trustworthy Designs”, Journal of Electronics Testing, Vol. 33, 2017. (SCI indexed)
  8. Bharat Garg, and G. K. Sharma, “ACM: An Energy-efficient Accuracy Configurable Multiplier for Error-resilient Applications”, Journal of Electronics Testing, Vol. 33, 2017 (SCI Indexed)
  9. Bharat Garg, Sunil Dutt, and G. K. Sharma "Bit-width-aware constant-delay run-time Accuracy Programmable Adder for error-resilient applications" Microelectronics Journal, Elsevier 2016, Vol. 50, pp. 1-7 (SCI indexed)
  10. Bharat Garg, and G. K. Sharma "A quality-aware Energy-scalable Gaussian Smoothing Filter for image processing applications" Microprocessors and Microsystems Elsevier (2016) Vol. 45, pp. 1-9. (SCI indexed)
  11. Neha Nawandar, Bharat Garg, and G. K. Sharma, “RICO: A low power Repetitive Iteration CORDIC for DSP applications in portable devices”, System Architecture, Elsevier 2016, Vol 70, pp. 82-92. (SCI indexed)
  12. Bharat Garg, and G. K. Sharma, "PAID: Process Aware Imprecise DCT Architecture Trading Quality for Energy Efficiency", Journal of Low Power Electronics, Vol. 11, No. 2 (2015): 121-132. (ESCI indexed)

International Conferences

  1. Vijaypal Rathor, Bharat Garg and G. K. Sharma, “An Energy−Efficient Trusted FSM Design Technique to Thwart Fault Injection and Trojan Attacks”, In VLSI Design (VLSID), 2015 31st Int. Conf. on, pp. 73-78. IEEE, 2018.
  2. Naushad Ali and Bharat Garg, “New Energy Efficient Reconfigurable FIR Filter Architecture and Its VLSI Implementation”, International Symposium on VLSI and Test (VDAT-2017), pp. 1-6, 2017.
  3. Bharat Garg, and G. K. Sharma, “Block Matching Algorithm for Deriving Quality-Tuneable Motion Estimation Architecture”, In Industrial and Information Systems (ICIIS-2016), 11th Int. Conference on, pp. 1-6, 2016.
  4. Bharat Garg, and G. K. Sharma, “Low Power Signal Processing via Approximate Multiplier for Error-Resilient Applications”, In Industrial and Information Systems (ICIIS-2016), 11th Int. Conference on, pp. 1-6, 2016.
  5. Bharat Garg, Sameer Yadav, and G. K. Sharma, “An Area and Performance Aware ECG Encoder Design for Wireless Healthcare Services”, International Symposium on VLSI Design and Test (VDAT-2016), pp. 1-6, 2016.
  6. Bharat Garg, Chaitanya Goteti, and G. K. Sharma, “A Low-Cost Energy Efficient Image Scaling Processor for Multimedia Applications”, International Symposium on VLSI Design and Test (VDAT-2016), pp. 1-6, 2016.
  7. Vikas Kaushal, Bharat Garg, Ankur Jaiswal, and G. K. Sharma "Energy Aware Computation Driven Approximate DCT Architecture for Image Processing" In VLSI Design (VLSID), 2015 28th Int. Conf. on, pp. 357-362. IEEE, 2015
  8. Ankur Jaiswal, Bharat Garg, Vikas Kaushal, and G. K. Sharma, “SPAA-Aware 2D Gaussian Smoothing Filter Design Using Efficient Approximation Techniques”, In VLSI Design (VLSID), 2015 28th International Conference on pp. 333-338, IEEE, 2015.
  9. Bharat Garg, Nitesh K. Bharadwaj, and G. K. Sharma "Energy scalable approximate DCT architecture trading quality via boundary error-resiliency", System-on-Chip Conference (SOCC), 27th IEEE Int., 2014, Las Vegas, USA.

Message to Students & Community

“Successful and unsuccessful people do not vary greatly in their abilities. They vary in their desires to reach their potential.” – John Maxwell.