Dr. Harpreet Vohra


Assistant Professor


VLSI Design



Contact No.


Area of interest :

System on-chip testing and Low power VLSI design.


Microprocessors, Electronics Engineering, Low power VLSI design, HDL, VLSI testing and verification, Digital circuits, Radar, satellite and navigation etc.

Publications and other Research Inputs


  1. Vohra H., Singh H.(2016) , Optimal Selective Count Compatible Runlength Encoding for SOC Test Data Compression, Journal of electronic testing, 32, 6, 735-747.
  2. H.Vohra and A.Singh, " Test data compression using hierarchica block merging technique", IET computers and digital techniques, 12(4), pp 176-185, July 2018.


  1. Vohra H., Singh H.(2016), Survey of System-on-Chip Modular Test Approach, Journal of VLSI Design Tools & Technology, 6(4).
  2. Chadha S., Vohra H.(2015), Enhanced Compression Code for SOC Test Data Volume Reduction, International Journal of Computational Engineering & Management,18 ( 3).
  3. Dewen N., Vohra H. (2015), Test Optimization of 2D SOC using Enhanced ACO Algorithm, International Journal of Computational Engineering & Management, 18 (3). 2.
  4. Dewen N., Agarwal P., Vohra H (2015). Test Time and Power Optimization of 2D SOCs Using GA and Greedy Algorithm, Journal of Power Electronics & Power Systems, 5 (2). 3.
  5. Dewen N. ,Vohra H. (2014) Test Scheduling of Core Based SOC Using Greedy Algorithm, International Journal of Engineering Research and Applications, 4 (9), 80-85. 4.
  6. Rani M., Vohra H.(2012), Design and Implementation of 64-Bit Execute Stage for VLIW Processor Architecture on FPGA, International Journal of Electronics Communication and Computer Technology (IJECCT), 2 (4), 2012

Description of Research Interests

SoC test cost minimization by Test volume compression and test architecture optimization. Low power VLSI design, Network on chip based SoC testing, low power VLSI design etc.