Mr. Subiman Chatterjee

Designation:

Visiting Assistant Professor

Specialization:

VLSI/ Digital Design

Email:

schatterjee@thapar.edu

Biography

Mr. Subiman Chatterjee is working with Electronics and Communication Engineering Department, Thapar Institute of Engineering and Technology, Patiala since July, 2019. He has completed M. Tech in the area of Digital Techniques and Instrumentation from the Department of Electronics Engineering, IIT (BHU), Varanasi and has recently submitted his thesis for Ph.D. degree from the same institute. His research interests include digital VLSI architectures for signal processing applications, image and video processing, DSP architectures.

Education

  • Ph.D. (IIT (BHU), Varanasi) in VLSI specialization
  • M. Tech (IIT (BHU), Varanasi) in Digital Techniques and Instrumentation, First class (8.23 CGPA)
  • B.Tech (W.B.U.T.) in Electronics and Communication Engineering, First class (7.91 DGPA)

Experience: Total Teaching Experience 3 years 10 month

  • July 2019 – Present: Visiting Assistant Professor, ECE Department, Thapar Institute of Engineering & Technology, Patiala, PB.
  • October 2010 – July 2014: Assistant Professor, ECE Department, Durgapur Institute of Advanced Technology & Management, Durgapur, WB.

Teaching Interests:

  • Digital VLSI
  • Digital Circuits
  • Signal and systems
  • Computer Architecture
  • RTL coding

Research Interest:

  • Image and Video processing
  • VLSI architectures for signal processing applications
  • DSP architectures
  • Biomedical / Biomechanics

Publications:

Journals

  1. S. Chatterjee and K. Sarawadekar, "An Optimized Architecture of HEVC Core Transform Using Real-Valued DCT Coefficients," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 12, pp. 2052-2056, Dec. 2018. [SCI Impact Factor 3.25].
  2. S. Chatterjee and K. Sarawadekar, "WHT and Matrix Decomposition-Based Approximated IDCT Architecture for HEVC," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 6, pp. 1043-1047, June 2019. [SCI Impact Factor 3.25].
  3. S. Chatterjee and K. Sarawadekar, "Approximated Core Transform Architectures for HEVC Using WHT-Based Decomposition Method," in IEEE Transactions on Circuits and Systems I: Regular Papers, Early Access, doi: 10.1109/TCSI.2019.2925268 [SCI Impact Factor 3.934].

International Conferences

  1. S. Chatterjee and K. P. Sarawadekar, "A low cost, constant throughput and reusable 8x8 DCT architecture for HEVC," 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), Abu Dhabi, 2016, pp. 1-4. doi: 10.1109/MWSCAS.2016.7869994
  2. S. Chatterjee and K. Sarawadekar, "Constant throughput HEVC core transform design," 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), Abu Dhabi, 2016, pp. 1-4. doi: 10.1109/MWSCAS.2016.7870111